FPGA Signal Processing VLCS01 Efficient FPGA-based VLSI architecture for detecting R-peaks in electrocardiogram signal by combining Shannon energy with Hilbert transform VLCS02 VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors VLCS03 A Universal String Matching Approach to Screen Content Coding VLCS04 A Nano-Watt ECG Feature Extraction Engine in 65nm Technology VLCS05 An Adaptive Mechanism for Designing Efficient Snoop Filters VLCS06 An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications VLCS07 Memory-Based Architecture for Multicharacter Aho–Corasick String Matching VLCS08 Modular Design of High-Efficiency Hardware Median Filter Architecture VLCS09 Design and Characterization of a Low-Cost FPGA-Based TDC VLCS10 Enhancing Sensor Pattern Noise via Filtering Distortion Removal for HD camera applications VLCS11 A Deterministic Approach to Detect Median Filtering in 1D Data for Motion estimation algorithm VLCS12 Fast Spectrum Analysis for an OFDR Using the FFT and SC Combination Approach for ECG signal analysis VLCS13 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation for low fiber optics communication VLCS14 Fault Tolerant Parallel FFTs architecture using an high speed parallel Error Correction Codes and Parseval Checks VLCS15 A Highly Customizable Low-Latency Communication MAC Architecture VLCS16 Source Coding and Preemphasis for Double-Edged Pulse width Modulation Serial Communication for double dynamic rate based wireless communication VLCS17 A Real-Time Fault aware Network-on-Chip Architecture With an Efficient GALS Implementation VLCS18 Assessing the Suitability of King Topologies for Interconnection Networks VLCS19 A New CDMA Encoding/Decoding Method for on-Chip Communication Network VLCS20 Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes Read More >>
