VLLP01

A Low Power and Low Area Router with Congestion-Aware Routing Algorithm for Spiking Neural Network Hardware Implementations

VLLP02

Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

VLLP03

Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches

VLLP04

High Throughput Low Complexity and Low Power ePiBM RS Decoder Using Fractional Folding

VLLP05

Data Retention based Low Leakage Power TCAM for Network Packet Routing

VLLP06

An Error Compensation Technique for Low-Voltage DNN Accelerators

VLLP07

Low-Power Ternary Multiplication Using Approximate Computing

VLLP08

Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design

VLLP09

Design of ultra-low power consumption approximate 4-2 compressors based on the compensation characteristic

VLLP10

Multi-Target Adaptive Reconfigurable Acceleration for Low-Power IoT Processing

VLLP11

Fast Binary Counters and Compressors Generated by Sorting Network

VLLP12

Low Power FPGA Based Implementation of CORDIC Architecture

VLLP13

Widely Tunable Low Pass gm? C Filter for Bio-medical Applications

VLLP14

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates for high-speed FPGA architectures